Project Staff Positions at Sardar Vallabhbhai National Institute of Technology
INR 58000
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Recruitment 2026: Project Staff Positions at Sardar Vallabhbhai National Institute of Technology (Department of Electronics Engineering)
The Department of Electronics Engineering at SVNIT Surat invites applications for Research Associate-I (RA-I) and Project Associate-I (PA-I) positions on a purely contractual basis under an ISRO-funded project.
Organization Details
Field | Details |
|---|---|
Institution | Sardar Vallabhbhai National Institute of Technology |
Department | Electronics Engineering |
Location | Surat, Gujarat, India |
Recruitment Type | Contract-Based |
Position Overview
Post Name | Number of Posts | Age Limit | Deadline |
|---|---|---|---|
Research Associate-I (RA-I) / Project Associate-I (PA-I) | 01 | Up to 35 Years | 01 June 2026 |
Project Details
Field | Details |
|---|---|
Project Title | Algorithm Development for Detection of Spoofing Signals in NavIC Receivers (FPGA-Based) |
Funding Agency | RESPOND, ISRO |
Duration | 3 Years or till project completion |
Roles & Responsibilities
Work on signal processing algorithms for NavIC systems
Develop FPGA-based solutions for spoofing detection
Participate in research, development, and implementation activities
Collaborate with project team and contribute to technical deliverables
Eligibility Criteria
Research Associate-I (RA-I)
Ph.D. in Electronics Engineering or equivalent
ORM.E./M.Tech in VLSI Design / Microelectronics / Electronics & Communication
Minimum 3 years of research/teaching/design experience
At least one SCI-indexed research publication
Project Associate-I (PA-I)
M.E./M.Tech in:
VLSI Design
Microelectronics
Electronics & Communication
or equivalent discipline
Salary Details
Position | Monthly Fellowship |
|---|---|
RA-I | INR 58,000 + 20% HRA |
PA-I | INR 31,000 + 20% HRA |
Duration
Initial appointment: 1 Year
Extendable up to 3 Years based on performance and project continuation
Application Process
Apply in prescribed format
Submit application as per institute guidelines
Ensure all supporting documents are attached
Important Dates
Event | Date |
|---|---|
Last Date to Apply | 01 June 2026 |
Important Instructions
Positions are purely contractual
Extension depends on performance and project duration
Only shortlisted candidates will be contacted
Age limit: Maximum 35 years
Final Note
This is a strong opportunity for candidates interested in VLSI, signal processing, and ISRO-funded research projects. Candidates with relevant expertise in NavIC systems and FPGA-based development are highly encouraged to apply.
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